The present application relates to semiconductor device manufacturing. More particularly, the present application relates to a self-aligned quadruple patterning (SAQP) process in which the width of a mandrel structure is modulated.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of CMOS devices. FinFETs are non-planar semiconductor devices which include at least one semiconductor fin protruding from a surface of a substrate. FinFETs can increase the on-current per unit area relative to planar field effect transistors.
Semiconductor fins are typically formed utilizing a sidewall image transfer (SIT) process since the same provides sub-lithographic line widths. In a typical SIT process, spacers are formed on each sidewall surface of a sacrificial mandrel that is formed on a topmost semiconductor material of a substrate. The sacrificial mandrel is removed and the remaining spacers are used as an etch mask to etch the topmost semiconductor material of the substrate. The spacers are then removed after each semiconductor fin has been formed.
One problem that is associated with forming semiconductor fins at tight pitch is that the process window for cutting of unwanted semiconductor fins is quite narrow. More specifically, the space available between fins at a tight pitch decreased the process window for placement of fin cut mask edge in between fins. As such, a method is needed that is capable of forming semiconductor fins in which the process window for cutting unwanted semiconductor fins is improved.